In the fabrication of low-voltage field-effect transistors, at least one body doping which corresponds to the doping of the channel zone is generated in the substrate. In a later step, the gate oxide is produced, typically through oxidation. In addition, the gate is produced, e.g., by means of applying and structuring a polysilicon layer, which is then structured, optionally together with the gate oxide.
Only subsequent to this structuring is the so-called LDD (=Lightly Doped Drain) implantation performed, with which a shallow doping is generated with a dopant of the second conductivity type in the source and drain region of low-voltage transistors and preferably also high-voltage transistors.
In a narrowed implantation region, the relatively high terminal doping of the second conductivity type then is produced for the source and drain connection, wherein the narrowed implantation region can be produced in a simple way by forming a spacer on the gate stack, which is formed from gate oxide and polysilicon gate.
For a semiconductor process with different gate oxide thicknesses, there is the problem that in the structuring of the gate stack, the gate oxide is not completely removed in the area of the LDD doping to be generated in case of a thicker gate oxide, in order not to generate undesired oxide ablation at other positions. In this way, LDD implantation can now be optimized for thin gate oxide thicknesses, as they are used for low-voltage transistors. For high-voltage transistors, which can have thicker gate-oxide thicknesses, however, the energy of LDD implantation is too small to penetrate through the thick gate oxide. This leads to a transistor with degraded electrical connection to the source, wherein the problem is aggravated with increasing thickness of the gate oxide.